Germanium channel MOSFETs: Opportunities and challenges

Introduction MOSFETs with a high-mobility channel are attractive candidates for advanced CMOS device structures, since it is becoming increasingly difficult to enhance Si CMOS performance through traditional device scaling. The lower effective mass and higher mobility of carriers in germanium (Ge) compared with silicon (Si) (2x higher mobility for electrons and 4x for holes) has prompted renewed interest in Ge-based devices for highperformance logic. Ge channel MOSFETs have been identified as one of the possible directions for channel engineering [1]. Recently, surface-channel Ge MOSFETs have been demonstrated using thin Ge oxynitride [2] or high-k dielectric [3–5] as the gate insulator. However, most of the devices reported have used relatively simple structures such as a ring-type gate structure for simplified integration, and devices usually have relatively large dimensions. In addition, the low bandgap of germanium (0.67 eV compared with 1.12 eV for Si) presents a device design challenge, while the much lower melting point (9348C compared with 1,4008C for Si) presents additional processing challenges for integrating Ge channel MOSFETs. To demonstrate state-of-the-art Ge channel devices, several key issues have to be addressed. This paper reviews the major integration challenges and mobility enhancement associated with Ge surfacechannel devices as well as strained Ge/SiGe channel devices. Ge surface-channel MOSFETs